Runtime Network-on-Chip Thermal and Power Balancing
Keywords:
Network-on-Chip (NoC), thermal balancing, power and thermal management, homogeneous MPSoC, runtimeAbstract
In Network-on-Chip (NoC), most thermal and peak power balancing methods are monitored by centralized power/thermal managers. This increases inter-core communication latency and imbalanced thermal distribution. These factors directly affect the hot spot formation caused by high power densities developed with increasing per-core transistor number. As a result, reliability decreases along with static power dissipation. This proposal aims to introduce hierarchical agents for balancing power and thermal distribution by manipulating system’s parameters such as power, thermal, voltage below the optimal values. As some level of control is applied, this proposal also targets to achieve network scalability by implementing some level of independencies; self-organize and self-optimize distributed agent in overcoming core-level homogeneous processing element (PE) thermal and power variations at runtime. The aims of this work are to significantly contribute to achieving runtime thermal and power balancing, power and thermal management and reducing thermal hot spot formation in NoC.References
M. B. Taylor et al., The RAW microprocessor: A computational fabric for software circuits and general-purpose programs, IEEE Micro, vol. 22, no. 22, pp. 145-162, Feb. 2005.
S. Pasricha, N. Dutt, On-chip communication architectures: System on chip interconnect, Morgan Kaufmann, April 2008.
M. Daneshtalab, A. Sobhani, A. Afzali-Kusha, O. Fatemi, and Z. Navabi, NoC hot spot minimization using AntNet dynamic routing algorithm, in IEEE International Conference on Application-specific Systems, Architectures and Processors ASAP '06, 2006.
S. Vangal et al., An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS, in Proceeding of Solid-State Circuits Conference, pp. 98-589, Feb. 2007.
E. J. Kim et al., “Energy optimization techniques in cluster interconnects,” in Proceeding of International Symposium of Low Power Electronic Design., pp. 459–464, August 2003.
L. Shang, L.-S. Peh, and N. K. Jha, Power-efficient interconnection networks: Dynamic voltage scaling with links, in IEEE Computer Architecture Letters, vol. 1 no. 1, p. 6-6, January 2002.
E. Beigne, F. Clermidy, S. Miermont, and P. Vivet, Dynamic voltage and frequency scaling architecture for units integration within a GALS NoC, in Proceeding of International Symposium of Network-on-Chip, pp. 129-138, 2008.
U. Y. Ogras, R. Marculescu, D. Marculescu, and E. G. Jung, Design and management of voltage-frequency island partitioned networks-on-chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 3 pp.330–341, March 2009.
S.-G. Yang, L. Li, Y.-A. Zhang, B. Zhang, and Y. Xu, A Power-aware adaptive routing scheme for network on a chip, 7th International Conference on ASIC, 2007. ASICON '07., pp. 1301–1304, Oct. 2007.
Z. ZhuanSun, K. Li, and Y. Shen, An efficient adaptive routing algorithm for application-specific network-on-chip, 3rd International Symposium on Parallel Architectures, Algorithms and Programming (PAAP), pp. 333–338, Dec. 2010.
C.C.N. Chu, and D.F. Wong, A matrix synthesis approach to thermal placement, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17 ,no. 11 pp. 1166–1174, Nov 1998.
M. D. Osterman, and M. Pecht, Placement for reliability and routability of convectively cooled PWBs, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 7 pp. 734–744, Jul 1990.
G. Chen, and S. Sapatnekar, Partition-driven standard cell thermal placement, Proceeding of ISPD, California, 2003.
D. Sylvester, D. Blaauw, and E. Karl, ElastIC: An adaptive self-healing architecture for unpredictable silicon, in IEEE Design & Test of Computers, vol. 23, no. 6, pp. 484–490, June 2006.
M.A. Al-Faruque, R. Krist, and J. Henkel, ADAM: Runtime agent-based distributed application mapping for on-chip communication, 45th ACM/IEEE Design Automation Conference, pp. 760–765, 2008.
M.A. Al-Faruque, J. Jahn, T. Ebi, and J. Henkel, Runtime thermal management using software agents for multi- and many-core architectures, in IEEE Design & Test of Computers, vol. 27, no. 6, pp. 58 – 68, Dec. 2010.
T. Ebi, M. Faruque, and J. Henkel, TAPE: Thermal-aware agent-based power economy multi/many-core architectures, IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers, pp. 302–309, Nov. 2009.
M. Nickray, M. Dehyadgari, and A. Afzali-kusha, Adaptive routing using context-aware agents for networks on chips, 4th IEEE International Design and Test Workshop (IDT), pp. 1 - 6, Nov. 2009.
W. Liu, J. Xu, X. Wu, Y. Ye, X. Wang, W. Zhang, M. Nikdast, and Z. Wang, A noc traffic suite based on real applications, in VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on, July 2011, pp. 66 – 71.
K.-Y. Jheng, C.-H. Chao, H.-Y. Wang, and A.-Y. Wu, Traffic thermal mutual coupling co-simulation platform for three-dimensional Network-on-Chip, in Proceeding of International Symposium on VLSI Design Automation and Test (VLSI-DAT), pp.135-138, April 2010.
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